1. Field of the Invention
The present invention relates to a pixel clock jitter reduction system and method for using same in a laser scanner. More particularly, the invention relates to a pixel clock jitter reduction system which uses a pixel clock signal and a start of scan signal to generate a new pixel clock and minimize pixel placement errors.
2. Description of the Related Art
The minimization of pixel placement errors in a raster scanner often poses difficult problems. Several factors which contribute to pixel placement errors are polygon motor speed fluctuations, optical anomalies, and pixel clock jitter. Prior systems have attempted to correct the polygon motor's speed fluctuations or the optical anomalies which are difficult to do.
A laser scanner, such as a raster output scanner is used to transmit image information to an imaging surface such as a recording medium. A light source, such as a laser light source, generates a light beam which is modulated in accordance with image information contained in video image signals or pixels. The modulated light beam is applied to a rotating, multi-faceted polygon which scans the modulated light beam across the image plane of the imaging surface. Each facet of the polygon is mirrored. The polygon is spun by a motor, the motor speed controlling image resolution in the direction of movement of the imaging surface (i.e., the Y-direction). Image resolution within a scan line (i.e., the X-direction) is a function of the image signal or pixel rate. The resolution in the direction of scan is determined by the image signal or pixel clock frequency. Each mirrored facet of the polygon provides image information corresponding to one horizontal scan line.
A number of systems which correct errors within the raster scanner are disclosed. U.S. Pat. No. 4,204,233 to Swager, assigned to Xerox Corporation, discloses a system for correcting a facet error which changes the rate of a bit clock based on errors of individual facets of a rotating polygon. At the time of a start-of-scan signal, a bit clock counter is reset. The error for a particular facet is determined by the interval between a scan line bit count output and an end-of-scan output. The facet error is represented by a binary number corresponding to the interval. The error for a particular facet is stored in a memory location corresponding to that facet. When the facet is utilized, the error previously stored in the memory location for that facet is used to control an oscillator so that the output frequency corresponds to the frequency required to compensate for velocity errors caused by that facet. After the facet is scanned, the error signal previously stored in memory for that facet is updated. During the time between the end-of-scan signal and the start-of-scan signal for a scan line, the error for the next facet is read out of memory. Because the pixel clock is itself used to measure the error, the reference allows only an accuracy to within plus or minus one pixel clock per scan line. Thus, if used in conjunction with a typical pixel clock which runs at up to a maximum of 100 MHz, the accuracy to which error correction can be achieved equates to only plus or minus 10 nanoseconds correction per scan line.
U.S. Pat. No. 4,349,847 to Traino, assigned to Xerox Corporation, discloses a raster output scanner having a movable imaging member and imaging beam for exposing the imaging member to create images thereon. A rotating polygon scans the beam across the imaging member in line-by-line fashion while the beam is modulated in accordance with pixels input thereto. A clock provides clock pulses for clocking the image pixels to the modulator. The polygon's velocity is controlled to maintain a predetermined velocity relationship between the imaging member and the polygon. Accordingly, the device compensates only for velocity variations.
U.S. Pat. No. 4,677,292 to Shimada discloses a method of generating image scanning clock signals in an optical scanning device wherein a plurality of clock signals are generated by a number of delay elements. One of the plurality of clock signals is selected based on the output of a light sensor. When the light sensor signal is detected, a latch circuit outputs a plurality of clock signals and a plurality of inverted clock signals. These inverted and non-inverted clock signals are fed to a clock selector circuit.
U.S. Pat. No. 4,571,623 to Schoon discloses a data clocking circuit wherein data clock signals are selected from an output of a stable clock in accordance with a program stored in a memory. A voltage controlled oscillator (VCO) provides the data clock signals and the VCO is controlled based on the difference in the accumulated count between the selected clock signals and the data clock signals. A lower frequency clock is used in conjunction with a simulated phase locked loop to simulate a higher frequency clock. A technique for smoothing out a data clock signal is provided.
U.S. Pat. No. 4,587,531 to Dangler discloses a clock signal producing apparatus wherein a start of scan (SOS) sensor and an end of scan (EOS) sensor are used to generate a clock signal. The signals from the SOS and EOS sensor are fed into the S and C inputs of an SR flipflop. The output of the SR flip-flop is fed into a NOR logic gate. The other input of the NOR gate in connected to a feedback loop. The output of the NOR gate is put through a delay. The output of the delay is fed back to the NOR gate and is also output as the clock signal.
U.S. Pat. No. 4,635,000 to Swanberg, assigned to Xerox Corporation, discloses a temporal pixel clock synchronization system with jitter correction wherein a timing error signal is generated based on the phase error between a start of scan signal and a start of pixel count signal and between an end of scan signal and an end of pixel count signal. There is also a facet error correction circuit.
While the related art attempts to compensate for various errors affecting pixel registration, the art does not compensate for pixel clock jitter errors by using the pixel clock signal and the start of scan signal to generate a new jitter-free pixel clock signal.